1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC), and especially relates to a protection circuit against latch-up in a multiple-supply integrated circuit, which is made of complementary metal-oxide semiconductor (CMOS).
2. Description of the Related Art
The CMOS process has become a major trend in the semiconductor process of IC fabrication. The CMOS process is characterized by the use of well structures, which can produce a minimum space taken by circuits by forming circuit components of different conductivity types on the same substrate. On the other hand, in order to increase suitability of ICs for applications in different systems, the CMOS IC is generally provided with a multiple-supply. FIG. 1 shows a cross-sectional diagram of a conventional CMOS IC, wherein an n-type substrate 10 and a p-well 20 respectively provide a p-type metal-oxide semiconductor field-effect transistor (PMOSFET) device and an n-type metal-oxide semiconductor field-effect transistor (NMOSFET) device. The PMOSFET device comprises a source/drain region, which is made of doped diffusion regions 22 and 24 in the substrate 10, and a gate 25 formed thereover. The NMOSFET device comprises a source/drain region, which is made of doped diffusion regions 14 and 12 in the p-well 20, and a gate 15 formed thereover. In the substrate 10, there is an n-doped diffusion region 27 to provide a bias voltage to the substrate 10; and in the p-well 20, there is a p-doped diffusion region 17 to provide a bias voltage to the p-well 20.
FIG. 2 shows an equivalent circuit of the CMOS structure. In FIG. 2, the PMOSFET has a source connected to a VDDL supply, a drain connected to a drain of the NMOSFET, a gate connected to a gate of the NMOSFET, and a base biased by a VDDH supply. The NMOSFET has a source and a base, both of them connected to a VSS supply. In other words, referring to FIG. 1, the gate 15 is connected with the gate 25; the n.sup.+ -type diffusion region 12 is connected to the p.sup.+ -type diffusion region 24; the p.sup.+ -type diffusion region 22 is connected to the VDDL supply; the n.sup.+ -type diffusion region 27 is connected the VDDH supply; and both of the n.sup.+ -type diffusion region 14 and the p.sup.+ -type diffusion region 17 are connected to the VSS supply. Because different supplies bias the p.sup.+ -type diffusion region 22 and the n.sup.+ -type diffusion region 27, both formed in the n-type substrate 10, a multiple-supply effect is produced. For example, the VDDL supply can supply 3.3V or 5V while the VDDH supply supplies 5V.
However, as shown in FIG. 1, a latch-up effect in the substrate may easily appear because of an undesirable power-on sequence for the device made by the foregoing process. When a 5V or 12V supply is switched on, the rise time from 0V to full amplitude (5V or 12V) takes about 5-100 ms, depending on the capacitors in the supply and the power supply values. As shown in FIG. 1, if the VDDL supply (3.3V) has been switched on, and the VDDH supply is fed into the circuit after a while. During the long rise time of the VDDH supply from 0V to about 2.7V, a considerably low bias voltage appears in the n-type well, and the p.sup.+ -type diffusion region 22 has been biased to about 3.3V by the VDDL supply. A forward bias appears at the pn junction that is formed by the n-type well 20 and the p.sup.+ -type diffusion region 22. A large amount of forward current, caused by this forward bias, will introduce a triggering effect for the pnpn structure in the substrate 10 and the p-well 20. Then a latch-up effect is produced. Once the latch-up effect is produced, permanent damage to the IC structure can not be avoided.
As a limitation of the current IC fabrication technology, it is difficult, even impossible, to fabricate devices having the same functions of the foregoing device by a method completely different from the conventional CMOS process. The latch-up effect accompanies the application of the CMOS well region technology and is difficult to prevent. This problem is more serious in the design for a multiple-supply IC. As a result, guard ring is used to overcome this problem. However, the guard ring can not absorb the forward current in IC since the guard ring is only designed located near the I/O pad. Hence, the effect of preventing latch-up is limited; and another problem is resulted from a large space occupied by the guard ring. Therefore, there is a need to improve the characteristics of the IC and prevent problems from the extremely high forward current in the IC based on the current CMOS technology.
FIG. 3A and FIG. 3B show a structure to prevent latch-up, disclosed in U.S. Pat. No. 4,871,927, which uses a MOSFET to prevent direct biasing with floating input terminal from incurring latch-up in a two-supply CMOS circuit. However, a pn junction between the well region and a diffusion region inside may be conducted at the same time to inject a large amount of carriers into the well region. Thus, this prior art can not completely prevent an occurrence of latch-up.